⚠️ Warning: This is a draft ⚠️
This means it might contain formatting issues, incorrect code, conceptual problems, or other severe issues.
If you want to help to improve and eventually enable this page, please fork RosettaGit's repository and open a merge request on GitHub.
MyHDL - From Python to Silicon!
MyHDL is an open source Python package that lets you go from Python to silicon. With MyHDL, you create a Python model of the hardware system, which you can then simulate, and validate, or export to Verilog or VHDL, and take it to a silicon implementation from there.
On www.myhdl.org you will find everything you need to get started - and to keep going - with MyHDL. Have fun!