Risc-V
{{language|Risc-V}}[https://riscv.org Risc-V] is an open source hardware instruction set architecture based on the principle of a '''R'''educed '''I'''nstruction '''S'''et '''C'''omputer. The project was started by the university of California, Berkeley in 2010. This site refers to the Risc-V assembly language. ([https://en.wikipedia.org/wiki/RISC-V#Software Wikipedia page]), Website: [https://riscv.org https://riscv.org].